The number of transistors on semiconductor chips will grow exponentially in the coming decades— this 1965 forecast made future Intel co-founder Gordon Moore famous. Far less attention was paid to another statement that could also be found in his article for the magazine Electronics: “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.”
Researchers and semiconductor manufacturers around the world are currently moving forward with this idea. They intend to distribute the numerous functions in the increasingly complex chips to smaller integrated circuits (ICs) that operate in concert. Experts call them chiplets—mini-ICs that can be connected to a complete system much like building blocks. They can each perform sub-functions of an overall system and can, for example, be used as a central processing unit (CPU), graphics processor (GPU), memory, digital interface to the outside world, or Wi-Fi transmitter and receiver.
Until recently, the trend was heading in the opposite direction
For decades, semiconductor manufacturers have integrated more and more functions on one and the same semiconductor board (known as a die) into highly complex systems-on-a-chip (SoC)—all thanks to Moore’s Law. However, companies are now encountering their limits, because the probability of defects increases as the dies get bigger, thereby greatly reducing the yield of functioning chips in production. That makes it very difficult to produce large SoCs economically—especially if the very latest manufacturing processes involving immense investment costs are being used to obtain a yield that is already relatively low to begin with.
“The issue of chiplets has been gaining momentum for several years now.” Dr. Michael Schiffer, Head of the Wafer Level System Integration department at the Fraunhofer Institute for Reliability and Microintegration IZM
“That’s why about 15 years ago we started looking for new approaches,” says Dr. Michael Schiffer, Head of the Wafer Level System Integration department at the Fraunhofer Institute for Reliability and Microintegration IZM in Berlin. “The issue has been gaining momentum for several years now because today, we have the technologies needed to connect chiplets to each other and because semiconductor manufacturers are now reaching their limits in terms of scrap costs.” Chiplets can solve the problem: If the functions of an SoC are distributed to smaller units, the yield on functioning ICs increases again.
Chiplets can solve the problem
If the functions of an SoC are distributed to smaller units, the yield on functioning ICs increases again. Chiplets have other advantages too. If each of them specializes in a single function, the optimum technology can be used for the production of each and every one: For example, you could use state-of-the-art manufacturing processes with the smallest transistors for the high-performance CPU and GPU chiplets, while simpler digital interface chiplets could be produced using older—and cheaper—processes. The same applies to the materials used: Silicon is the best choice for CPU and GPU dies, while gallium arsenide, silicon-germanium, or silicon carbide is the best choice for high-frequency and high-performance chiplets; indium phosphide is most suited to optoelectronic components. “This maximizes the performance of the individual chiplets and improves their efficiency,” says Schiffer.
However, the specialized mini-chips must be connected to form a complete system. For this purpose, a silicon interposer, as it is known, is generally used as a location for the chiplets. Either the interposer is a thin silicon plate, into which only copper tracks are inserted for the electrical connection of the chips, or the silicon interposer itself can contain an electronic circuit that actively conducts the chiplet signals, thereby significantly reducing lag times. “Glass is also a potential material for high-frequency applications while organic substances are also conceivable as a material for the interposer, but these cannot compete with silicon interposers in terms of structure sizes,” explains Schiffer.
However, the potential of the chiplet idea can only be fully exploited if the components made by different manufacturers can be combined into a complete system without any problems. In the future, the Universal Chiplet Interconnect Express (UCIe) communication standard plans to make this possible—similar to Peripheral Component Interconnect Express (PCIe), which today is used to connect diverse peripheral devices such as hard disks or graphics cards to the chip set of a processor in a PC. UCIe is backed by chip developers such as AMD, ARM, Intel, Google Cloud, Meta, Microsoft, Qualcomm, and Samsung, as well as TSMC, which is the world’s largest contract manufacturer of semiconductors. As an alternative, the Open Compute Project (OCP) has introduced the Bunch of Wires (BoW) standard. Members of the OPC include operators of large data centers such as Google, Meta, and Microsoft.
Chiplet standard for vehicles
“Both standards are designed for the exchange of very large amounts of data,” says Andy Heinig, Group Manager System Integration at the Fraunhofer Institute for Integrated Circuits IIS in Dresden. “For automotive applications, however, additional analog interfaces would be needed in order to be able to assemble, say, a radar from different chiplets.”
Together with OEMs and suppliers, the researchers at IIS intend to develop a standard that is tailor-made for use in vehicles. Although a standard has yet to be established, it is clear to Heinig that chiplets will play an important role in vehicles in the future: “Autonomous driving in particular needs a huge amount of processing power, although the exact requirements will depend largely on the level of automation being aimed for. In the future, OEMs could design the electronics optimally for their individual models or for the different equipment variants by using chiplets.”
“Additional analog interfaces are needed for automotive applications.” Andy Heinig, Group Manager System Integration at the Fraunhofer Institute for Integrated Circuits
This scalable modular system also caters perfectly to the car manufacturers’ platform concept. Prof. Steffen Paul, head of the Communication Electronics Working Group at the University of Bremen, is investigating how such a vehicle system might look in tandem with industrial and academic project partners. As he, too, stresses: “Chiplets mean that system configurations can be flexibly adapted to the requirements of vehicles.” His team demonstrates this using the example of a 77-gigahertz radar for autonomous driving. The analog part is divided into several chiplets, which work both as an oscillator and as a transmitter/receiver, and are housed on a silicon interposer. Depending on the required number of antennas, two or four transceiver chiplets are integrated into the system.
The digital part that processes the signals can consist of up to eight chiplets—depending on the complexity of the evaluation algorithms used. In addition to the greater flexibility attained by combining different calculation engines, Professor Paul sees another advantage in the chiplet approach: Improved protection of intellectual property. “Partitioning the functions into smaller units makes it much more difficult for competitors to determine how the overall system works. In addition, critical functions such as encryption can be developed separately on a chiplet – in a high-security area and kept separate from the development of the remaining logic,” explains the expert.
Key factor for the future
“Chiplets are currently used in markets such as data centers, mobile devices, networks, and storage,” says Tom Hackenberg, Principal Analyst for Computing and Software at technology consulting firm Yole Intelligence. “With the emergence of powerful heterogeneous processors in driver assistance systems, however, they are becoming a key factor in future electronic systems in vehicles. That’s why many car chip manufacturers support the standardization of the chiplet.” Once more, one of Gordon Moore’s predictions may have hit the bullseye.
Info
Text first published in the Porsche Engineering Magazine, issue 1/2023
Text: Christian Buck
Illustrations: Oriana Fenwick
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